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Data Sheet
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CDK1305
10-bit, 40 MSPS 175mW A/D Converter
CDK1305 10-bit, 40 MSPS 175mW A/D Converter
features n 40 MSPS converter n 175mW power dissipation n On-chip track-and-hold n Single +5V power supply n TTL/CMOS outputs n 5pF input capacitance n Tri-state output buffers n High ESD protection: 3,500V minimum n Selectable +3V or +5V logic I/O applications n All high-speed applications where low power dissipation is required n Video imaging n Medical imaging n Radar receivers n IR imaging n Digital communications
General Description
The CDK1305 is a 10-bit, low power analog-to-digital converter capable of minimum word rates of 40 MSPS. The on-chip track-and-hold function assures very good dynamic performance without the need for external components. The input drive requirements are minimized due to the CDK1305 low input capacitance of only 5pF. Power dissipation is extremely low at only 175mW typical at 40 MSPS with a power supply of +5.0V. The digital outputs are +3V or +5V, and are user selectable. The CDK1305 is pin-compatible with an entire family of 10-bit, CMOS converters (CDK1304/05/06), which simplifies upgrades. The CDK1305 has incorporated proprietary circuit design* and CMOS processing technologies to achieve its advanced performance. Inputs and outputs are TTL/CMOS-compatible to interface with TTL/CMOS logic systems. Output data format is straight binary. The CDK1305 is available in 28-lead SOIC and 32-lead small (7mm square) TQFP packages over the commercial temperature range.
Block Diagram
REV 1A
Ordering Information
Part Number CDK1305CSO28 CDK1305CSO28_Q CDK1305CTQ32 CDK1305CTQ32_Q Package SOIC-28 SOIC-28 TQFP-32 TQFP-32 Pb-Free Yes No Yes No RoHS Compliant Yes No Yes No Operating Temperature Range 0C to +70C 0C to +70C 0C to +70C 0C to +70C Packaging Method Rail Rail Rail Rail
Moisture sensitivity level for SOIC-28 is MSL-1 and TQFP is MSL-3. (c)2008 CADEKA Microcircuits LLC www.cadeka.com
Data Sheet
Pin Configuration SOIC-28 TQFP-32
CDK1305 10-bit, 40 MSPS 175mW A/D Converter
CDK1305
CDK1305
Pin Assignments
SOIC-28 1,8 2 3 5 6 9 7 10 11 12 13 15 16-20, 23-27 28 14 22 21 4 TQFP-32 3,4,28,29 30 31 32 1 5 2 6,7 8,9 10,11 12 14 15-19, 22-26 27 13 21 20 - Pin Name AGND VRHF VRHS VRLS VRLF VCAL VIN AVDD DVDD DGND CLK EN D0-D9 D10 DAV OVDD OGND N/C Analog Ground Reference High Force Reference High Sense Reference Low Sense Reference Low Force Calibration Reference Analog Input Analog VDD Digital VDD Digital Ground Input Clock CLK = FS (TTL) Output Enable Tri-State Data Output, (D0 = LSB) Tri-State Output Overrange Data Valid Output Digital Output Supply Digital Output Ground No Connect Description
REV 1A
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2
Data Sheet
Absolute Maximum Ratings
The safety of the device is not guaranteed when it is operated above the "Absolute Maximum Ratings". The device should not be operated at these "absolute" limits. Adhere to the "Recommended Operating Conditions" for proper device function. The information contained in the Electrical Characteristics tables and Typical Performance plots reflect the operating conditions noted on the tables and plots.
CDK1305 10-bit, 40 MSPS 175mW A/D Converter
Parameter Supply Voltages AVDD DVDD Input Voltages Analog input VRef CLK input AVDD - DVDD AGND - DGND Digital Outputs
Min
Max +6 +6
Unit V V V V V mV mV mA
-0.5 0 -100 -100
AVDD +0.5 AVDD VDD 100 100 10
Reliability Information
Parameter Storage Temperature Range Min -65 Typ Max +150 Unit C
Recommended Operating Conditions
Parameter Operating Temperature Range Junction Temperature Range Lead Temperature (soldering 10 seconds) Min 0 Typ Max +70 +175 +300 Unit C C C
REV 1A
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3
Data Sheet
Electrical Characteristics
(TA = TMin to TMax, AVDD = DVDD = OVDD = +5V, VIN = 0 to 4V, clk = 40 MSPS, VRHS = 4V, VRLS = 0V; unless otherwise noted)
symbol parameter
Resolution
conditions
Min
10 -0.5 -1.0
typ
Max
units
bits
DC Performance
CDK1305 10-bit, 40 MSPS 175mW A/D Converter
DLE ILE
Differential Linearity Error(1) Integral Linearity Error No Missing Codes
(1)
+0.5 +1.0 Guaranteed
LSB LSB
Analog Input
Input Voltage Range(1) Input Resistance(2) Input Capacitance Input Bandwidth Gain Error Offset Error Small Signal VRLS 50 5 250 2.0 2.0 300 Small Signal VRLS(2) VRHS(2) Voltage Range VRHS - VRLS (VRHF - VRHS) (VRLS - VRLF) 0 3.0 4.0 90 75 15 20 40 2 12 4.0 30 IN = 3.58MHz IN = 10.3MHz IN = 3.58MHz(1) IN = 10.3MHz
(1)
VRHS
V k pF MHz LSB LSB
Reference Input
Resistance(1) Bandwidth 500 150 2.0 AVDD 600 MHz V V V mV mV CLK Cycle CLK Cycle MHz MHz CLK Cycle ns pspp Bits Bits dB dB dB dB dB dB
Reference Settling Time
VRHS VRLS
Conversion Characteristics
Maximum Conversion Rate(1) Minimum Conversion Rate(2) Pipeline Delay (Latency)(2) Aperture Delay Time Aperture Jitter Time
REV 1A
Dynamic Performance
ENOB SNR Effective Number of Bits Signal-to-Noise Ratio w/o Harmonics 8.5 8.3 52 51 55 52 51 49 54 52 61 53 54 52
THD
Total Harmonic Distortion
IN = 3.58MHz(1) , 9 distortion bins from 1024 pt FFT IN = 10.3MHz(1) , 9 distortion bins from 1024 pt FFT IN = 3.58MHz(1) IN = 10.3MHz(1)
SINAD
notes:
Signal-to-Noise and Distortion
1. 100% production tested at +25C. 2. Parameter is guaranteed (but not tested) by design and characterization data.
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Data Sheet
Electrical Characteristics
(TA = TMin to TMax, AVDD = DVDD = OVDD = +5V, VIN = 0 to 4V, clk = 40 MSPS, VRHS = 4V, VRLS = 0V; unless otherwise noted)
symbol
SFDR
parameter
Spurious Free Dynamic Range Differential Phase Differential Gain
conditions
IN = 1MHz
Min
typ
63 0.3 0.3
Max
units
pspp deg
CDK1305 10-bit, 40 MSPS 175mW A/D Converter
% V 0.8 V A A pF V 0.4 V ns ns ns ns 5.0 V V V mA mA mW +10 +10
Digital Inputs
Logic "1" Voltage(1) Logic "0" Voltage(1) Maximum Input Current Low Input Capacitance
(1)
2.0 -10 -10 +5 IOH = 0.5mA IOL = 1.6mA 15pF load 15pF load 20pF load, TA = 25C 50pF load over temp 3.0 10 10 10 22 3.5
Maximum Input Current High(1)
Digital Outputs
Logic "1" Voltage(1) Logic "0" Voltage(1) TR TF Rise Time Fall Time Output Enable to Data Output Delay
Power Supply Requirements
OVDD DVDD AVDD AIDD DIDD Digital Voltage Current(1) Power Dissipation(1)
notes: 1. 100% production tested at +25C. 2. Parameter is guaranteed (but not tested) by design and characterization data.
Digital Voltage Supply
(2)
4.75 4.75
5.0 5.0 17 18 175
5.25 5.25 22 23 225
REV 1A
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Data Sheet
Typical Performance Characteristics
(TA = TMin to TMax, AVDD = DVDD = OVDD = +5V, VIN = 0 to 4V, clk = 40 MSPS, VRHS = 4V, VRLS = 0V; unless otherwise noted) performance vs. sample rate
63 62
THD
snr, tHD, sinaD vs. input freq.
80
CDK1305 10-bit, 40 MSPS 175mW A/D Converter
Performance (dB)
61 60 59 58 57 56 55 54 0
IN = 1MHz SNR SINAD
SNR, THD, SINAD (dB)
70 60 50 40 30 20 10 0 10 100 1000
SINAD SNR THD
5
10
15
20
25
30
35
40
Sample Rate (MSPS)
Input Frequency (MHz)
snr, tHD vs. input range
70 60
THD SNR
power Dissipation vs. sample rate
220 200
SNR, THD (dB)
50 40 30 20 10 0 1.0
Total Power (mV)
180 160 140 120 100 80
VIN = 0V
VIN = 4V Sinewave
IN = 1MHz S = 40 MSPS
REV 1A
1.5
2.0
2.5
3.0
3.5
4.0
4.5
5.0
60
10
15
20
25
30
35
40
45
Input Range (V)
Sample Rate (MSPS)
spectral response
0
IN = 1.035MHz S = 40 MSPS
performance vs. temperature
62 60
THD
Performance (dB)
Amplitude (dB)
-30
58 56 54
SINAD IN = 1MHz S = 40 MSPS
-60
SNR
-90
52 -120 50
0
1
2
3
4
5
6
7
8
9
10
-40
-20
0
20
40
60
80
100
Input Frequency (MHz)
Temperature (C)
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6
Data Sheet
Specification Definitions
aperture Delay Aperture delay represents the point in time, relative to the rising edge of the CLOCK input, that the analog input is sampled. aperture Jitter The variations in aperture delay for successive samples. Differential Gain (DG) A signal consisting of a sine wave superimposed on various DC levels is applied to the input. Differential gain is the maximum variation in the sampled sine wave amplitudes at these DC levels. Differential phase (Dp) A signal consisting of a sine wave superimposed on various DC levels is applied to the input. Differential phase is the maximum variation in the sampled sine wave phases at these DC levels. effective number of Bits (enoB) SINAD = 6.02N + 1.76, where N is equal to the effective number of bits. N = SINAD - 1.76 6.02 input Bandwidth Small signal (50mV) bandwidth (3dB) of analog input stage. Differential linearity error (Dle) Error in the width of each code from its theoretical value. (Theoretical = VFS/2N) integral linearity error (ile) Linearity error refers to the deviation of each individual code (normalized) from a straight line drawn from -FS through +FS. The deviation is measured from the edge of each particular code to the true straight line. output Delay Time between the clock's triggering edge and output data valid. overvoltage recovery time The time required for the ADC to recover to full accuracy after an analog input signal 125% of full scale is reduced to 50% of the full-scale value. signal-to-noise ratio (snr) The ratio of the fundamental sinusoid power to the total noise power. Harmonics are excluded. signal-to-noise and Distortion (sinaD) The ratio of the fundamental sinusoid power to the total noise and distortion power. total Harmonic Distortion (tHD) The ratio of the total power of the first 9 harmonics to the power of the measured sinusoidal signal. spurious free Dynamic range (sfDr) The ratio of the fundamental sinusoidal amplitude to the single largest harmonic or spurious signal.
CDK1305 10-bit, 40 MSPS 175mW A/D Converter
REV 1A
Figure 1. Timing Diagram 1
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Data Sheet
Table 1. Timing Parameters
Description
Conversion Time CLK Period CLK High Duty Cycle CLK Low Duty Cycle CLK to Output Delay (15pF load) CLK to DAV
sym
tC tCLK tCH tCL tOD tS
Min
tCLK 40 40 40
typ
Max units
ns ns
50 50 17 10
60 60
% % ns ns
CDK1305 10-bit, 40 MSPS 175mW A/D Converter
Figure 2. Timing Diagram 2
CDK1305
REV 1A
Figure 3. Typical Interface Circuit Diagram
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Data Sheet
Typical Interface Circuit
Very few external components are required to achieve the stated device performance. Figure 2 shows the typical interface requirements when using the CDK1305 in normal circuit operation. The following sections provide descriptions of the major functions and outline critical performance criteria to consider for achieving the optimal device performance.
n
Since only 16 comparators are used, a huge power savings is realized. The auto-zero operation is done using a closed loop system that uses multiple samples of the comparator's response to a reference zero. The auto-calibrate operation, which calibrates the gain of the MSB reference and the LSB reference, is also done with a closed loop system. Multiple samples of the gain error are integrated to produce a calibration voltage for each ADC section. Capacitive displacement currents, which can induce sampling error, are minimized since only one comparator samples the input during a clock cycle. The total input capacitance is very low since sections of the converter that are not sampling the signal are isolated from the input by transmission gates.
n
CDK1305 10-bit, 40 MSPS 175mW A/D Converter
n
Power Supplies And Grounding
Cadeka suggests that both the digital and the analog supply voltages on the CDK1305 be derived from a single analog supply as shown in Figure 2. A separate digital supply should be used for all interface circuitry. Cadeka suggests using this power supply configuration to prevent a possible latch-up condition on powerup.
n
n
Operating Description
The general architecture for the CMOS ADC is shown in the Block Diagram. The design contains 16 identical successive approximation ADC sections, all operating in parallel, a 16-phase clock generator, an 11-bit 16:1 digital output multiplexer, correction logic, and a voltage reference generator that provides common reference levels for each ADC section. The high sample rate is achieved by using multiple SAR ADC sections in parallel, each of which samples the input signal in sequence. Each ADC uses 16 clock cycles to complete a conversion. The clock cycles are allocated as shown in Table 2. Table 2. Clock Cycles
clock 1 2 3 4 5-15 16 operation Reference zero sampling Auto-zero comparison Auto-calibrate comparison Input sample 11-bit SAR conversion Data transfer
Voltage Reference
The CDK1305 requires the use of a single external voltage reference for driving the high side of the reference ladder. It must be within the range of 3V to 5V. The lower side of the ladder is typically tied to AGND (0.0V), but can be run up to 2.0V with a second reference. The analog input voltage range will track the total voltage difference measured between the ladder sense lines, VRHS and VRLS. Force and sense taps are provided to ensure accurate and stable setting of the upper and lower ladder sense line voltages across part-to-part and temperature variations. By using the configuration shown in Figure 4, offset and gain errors of less than 2 LSB can be obtained. In cases where wider variations in offset and gain can be tolerated, VREF can be tied directly to VRHF, and AGND can be tied directly to VRLF as shown in Figure 5. Decouple force and sense lines to AGND with a 0.01F capacitor (chip cap preferred) to minimize high-frequency noise injection. If this simplified configuration is used, the following considerations should be taken into account. The reference ladder circuit shown in Figure 5 is a simplified representation of the actual reference ladder with force and sense taps shown. Due to the actual internal structure of the ladder, the voltage drop from VRHF to VRHS is not equivalent to the voltage drop from VRLF to VRLS.
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REV 1A
The 16-phase clock, which is derived from the input clock, synchronizes these events. The timing signals for adjacent ADC sections are shifted by one clock cycle so that the analog input is sampled on every cycle of the input clock by exactly one ADC section. After 16 clock periods, the timing cycle repeats. The latency from analog input sample to the corresponding digital output is 12 clock cycles.
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9
Data Sheet
a specific case. VREF of 4.0V is applied to VRHF, and VRLF is tied to AGND. A 90mV drop is seen at VRHS (= 3.91V), and a 75mV increase is seen at VRLS (= 0.075V).
Analog Input
VIN is the analog input. The input voltage range is from VRLS to VRHS (typically 4.0V) and will scale proportionally with respect to the voltage reference. (See Voltage Reference section.) The drive requirements for the analog inputs are very minimal when compared to most other converters due to the CDK1305 extremely low input capacitance of only 5pF and very high input resistance of 50k. The analog input should be protected through a series resistor and diode clamping circuit as shown in Figure 7.
CDK1305 10-bit, 40 MSPS 175mW A/D Converter
Figure 4. Ladder Force/Sense Circuit
REV 1A
Figure 6. Recommended Input Protection Circuit
Calibration
The CDK1305 uses an auto-calibration scheme to ensure 10-bit accuracy over time and temperature. Gain and offset errors are continually adjusted to 10-bit accuracy during device operation. This process is completely transparent to the user. Upon powerup, the CDK1305 begins its calibration algorithm. In order to achieve the calibration accuracy required, the offset and gain adjustment step size is a fraction of a 10-bit LSB. Since the calibration algorithm is an oversampling process, a minimum of 10,000 clock cycles are required. This results in a minimum calibration time upon powerup of 250s (for a 40MHz clock). Once calibrated, the CDK1305 remains calibrated over time and temperature. Since the calibration cycles are initiated on the rising edge of the clock, the clock must be continuously applied for the CDK1305 to remain in calibration.
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Figure 5. Reference Ladder Circuit Typically, the top side voltage drop for VRHF to VRHS will equal: VRHF - VRHS = 2.25 % of (VRHF - VRLF) (typical) and the bottom side voltage drop for VRLS to VRLF will equal: VRLS - VRLF = 1.9 % of (VRHF - VRLF) (typical) Figure 5 shows an example of expected voltage drops for
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10
Data Sheet
Input Protection
All I/O pads are protected with an on-chip protection circuit shown in Figure 6. This circuit provides ESD robustness to 3.5kV and prevents latch-up under severe discharge conditions without degrading analog transition times.
Digital Outputs
The digital outputs (D0-D10) are driven by a separate supply (OVDD) ranging from +3 V to +5 V. This feature makes it possible to drive the CDK1305 TTL/CMOS compatible outputs with the user's logic system supply. The format of the output data (D0-D9) is straight binary. (See Table 3.) The outputs are latched on the rising edge of CLK. These outputs can be switched into a tri-state mode by bringing EN high. Table 3. Output Data Information
Analog Input +F.S. + 1/2 LSB +F.S. -1/2 LSB +1/2 F.S. +1/2 LSB 0.0V Overrange D10 1 0 0 0 0 Output Code D9-D0 1111111111 1 1 1 1 1 1 1 1 1O OO OOOO OOOO 000000000O 0000000000
CDK1305 10-bit, 40 MSPS 175mW A/D Converter
(O indicates the flickering bit between logic 0 and 1.)
Overrange Output
Figure 7. On-Chip Protection Circuit The Overrange Output (D10) is an indication that the analog input signal has exceeded the positive fullscale input voltage by 1 LSB. When this condition occurs, D10 will switch to logic 1. All other data outputs (D0 to D9) will remain at logic 1 as long as D10 remains at logic 1. This feature makes it possible to include the CDK1305 in higher resolution systems.
Power Supply Sequencing Considerations
All logic inputs should be held low until power to the device has settled to the specific tolerances. Avoid power decoupling networks with large time constants that could delay VDD power to the device.
REV 1A
Clock Input
The CDK1305 is driven from a single-ended TTL-input clock. Because the pipelined architecture operates on the rising edge of the clock input, the device can operate over a wide range of input clock duty cycles without degrading the dynamic performance.
Evaluation Board
The TBD evaluation board is available to aid designers in demonstrating the full performance of the CDK1305. This board includes a reference circuit, clock driver circuit, output data latches, and an on-board reconstruction of the digital data. An application note describing the operation of this board, as well as information on the testing of the CDK1305, is also available. Contact the factory for price and availability.
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11
Data Sheet
Mechanical Dimensions
SOIC-28 Package
Inches
Symbol Min Max
CDK1305 10-bit, 40 MSPS 175mW A/D Converter
Millimeters
Min Max
IH
A B C D E F G H I
0.699 0.709 0.005 0.011 0.050 Typ 0.018 Typ 0.0077 0.0083 0.096 0.090 0.031 0.039 0.396 0.416 0.286 0.292
17.75 18.01 0.13 0.28 1.27 BSC 0.46 BSC 0.20 0.21 2.29 2.44 0.79 0.99 10.06 10.57 7.26 7.42
A F B C H D
E
G
TQFP-32 Package
A B G
REV 1A
H
Symbol
CD
I J E F
A B C D E F G H I J K L
0.346 0.272 0.346 0.272 0.031 0.012 0.053 0.002 0.037 0 0.020
Min
Inches
0.362 0.280 0.362 0.280 Typ 0.016 0.057 0.006 0.041 0.007 7 0.030
Max
8.80 9.20 6.90 7.10 8.80 9.20 6.90 7.10 0.80 BSC 0.30 0.40 1.35 1.45 0.05 0.15 0.95 1.05 0.17 0 7 0.50 0.75
Min
Millimeters
Max
K L
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CADEKA, the CADEKA logo design, COMLINEAR and the COMLINEAR logo design are trademarks or registered trademarks of CADEKA Microcircuits LLC. All other brand and product names may be trademarks of their respective companies. CADEKA reserves the right to make changes to any products and services herein at any time without notice. CADEKA does not assume any responsibility or liability arising out of the application or use of any product or service described herein, except as expressly agreed to in writing by CADEKA; nor does the purchase, lease, or use of a product or service from CADEKA convey a license under any patent rights, copyrights, trademark rights, or any other of the intellectual property rights of CADEKA or of third parties. Copyright (c)2008 by CADEKA Microcircuits LLC. All rights reserved.
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